1. Field of the Invention
The present invention relates to a semiconductor device and can be suitably used, for example, in a semiconductor device with a sense amplifier.
2. Description of the Background Art
Conventionally, semiconductor devices are provided with sense amplifiers that amplify a minute voltage read out from a memory cell to a power supply voltage. A variety of offset compensation circuits for compensating for the offset voltage of sense amplifiers have been proposed.
In the offset compensation circuit according to M.-F. Chang, S.-J. Shen, C.-C. Liu, C.-W. Wu, Y.-F. Lin, S.-C. Wu, C.-E. Huang, H.-C. Lai, Y.-C. King, C.-J. Lin, H.-J. Liao, Y.-D. Chih, H. Yamauchi, “An Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100 nA-Cell-Current Nonvolatile Memory”, IEEE International Solid-State Circuits Conference, Dig. of Tech. Papers, pp. 206-208, 2011, first, two P-channel MOS transistors of a sense amplifier are diode connected, cell current and reference current are fed to the two transistors, respectively, and the gate-source voltages of the two transistors are held by respective two capacitors. Here, the gate-source voltages obtained by correcting the difference between the threshold voltages of the two transistors are held by the two capacitors. Next, the two transistors are cross-coupled to start a sense operation.
An offset compensation circuit in Japanese Patent Laying-Open No. 2011-175689 has a sense amplifier connected between two data buses. After the two data buses are precharged to a predetermined voltage, electric charge of one data bus is distributed to a capacitor to reduce the voltage of the data bus, so that the sense amplifier is activated to store a read data signal. This operation is performed with the capacitance value of the capacitor being changed to a plurality of stages for each data bus. The capacitance value of the capacitor connected to the data bus in a read operation is determined based on a plurality of stored read data signals.
In the above-noted non-patent document, two capacitors are charged every read operation, thereby decelerating the read speed.
In Japanese Patent Laying-Open No. 2011-175689, the read data signals are stored with the capacitance value of the capacitor being changed to a plurality of stages for each data bus, and the capacitance value of the capacitor is determined based on a plurality of stored read data signals. This leads to complication of the configuration.